Semiconductor Circuit Device

ABSTRACT

A semiconductor circuit device is provided which can attain more stable operations against noise in a data communication system without increasing the power consumption of an overall system, thereby improving the reliability of data communication. For a demodulation baseband signal (S 11 ) obtained by performing digital processing on an output signal (S 6 ) from an AD converter ( 6 ), the maximum value (S 12 ) and the minimum value (S 13 ) are detected as digital values by a maximum value holding circuit ( 11 ) and a minimum value holding circuit ( 12 ), an averaging circuit ( 13 ) obtains an average value (intermediate value) of the maximum value and the minimum value and detects a frequency offset amount (S 14 ), and the frequency offset amount is fed back to a threshold value of data decision ( 14 ), so that binarized demodulation data (S 15 ) is outputted in which the offset of the demodulation baseband signal is corrected.

FIELD OF THE INVENTION

The present invention relates to a semiconductor circuit device fordetecting and correcting a frequency offset generated between a transmitside and a receive side in data communication through FSK radiocommunication using an FSK signal, which is one of frequency modulationsignals.

BACKGROUND OF THE INVENTION

Conventionally, data communication for wirelessly transmitting variousdata through FSK radio communication using an FSK (frequency shiftkeying) signal is widely used as a system of data communication. The FSKsignal is one of FM (frequency modulation) signals.

In the data communication through FSK radio communication, when data istransmitted, a high-frequency signal is transmitted as a radio wave, thehigh-frequency signal having been frequency-modulated byfrequency-shifting a carrier so as to correspond to 1 and 0 of a digitalsignal of the data. When the high-frequency signal is received by an FSKreceiver and the transmitted data is demodulated, the frequencycomponents of a demodulation baseband signal having beenvoltage-converted by an F-V converter circuit are compared with eachother by a comparator to determine a digital value, and the originaldata is obtained based on the digital value.

In the frequency modulation system, between a transmit side and areceive side, a frequency offset occurs due to a frequency generationerror on a quartz radiator, a local oscillator (hereinafter, referred toas PLL), and the like of the transmit side and receive side. Thefrequency offset becomes a DC offset component when frequency-voltageconversion is performed to obtain a demodulation baseband signal.

In conventional FSK receivers, FSK demodulation is performed in ananalog manner, and thus a frequency offset is equivalent to afluctuation in the reference voltage of a comparator for data decision.Further, due to a frequency offset, the frequency of a carrier isshifted close to the cutoff frequency of a filter when the carrierpasses through the filer. Thus, particularly in the case ofcommunications in a narrow transmission band, the attenuation of thefilter exercises considerable influence. These factors have seriouslyadverse effects on the receiving characteristic of the FSK receivers.

As described above, in the conventional FSK receivers (for example,Japanese Patent Laid-Open No. 2000-349840), FSK demodulation isperformed in an analog manner. In this case, a demodulation basebandsignal having undergone frequency-voltage conversion is extracted by Ccoupling and a DC offset component on the demodulation baseband signalis removed, so that a demodulation error caused by a DC offset iscorrected and the adverse effects on the receiving characteristic areavoided.

Further, a difference is obtained between the signal where the DC offsetcomponent on the demodulation baseband signal is removed by C couplingand a demodulation baseband signal with a DC offset before C coupling,so that the DC offset component is detected on the demodulation basebandsignal having undergone frequency-voltage conversion. The referencevoltage in a comparator for data decision is corrected according to anoffset amount and a frequency offset is equally corrected.

However, in the conventional method of correcting a frequency offset,all circuits including detectors and correcting units conventionallyhave analog configurations in the FSK receivers. In this case, there aremany variations in operating characteristics among the circuits, theaccuracy of detecting a DC offset component from a demodulation basebandsignal is reduced by noise, and thus a DC offset cannot be accuratelydetected or corrected. Consequently, operations become susceptible tonoise and become less stable in a data communication system through FSKradio communication.

Once a malfunction occurs due to noise, the circuits may enter anoscillation state. Thus, the power consumption of an overall systemincreases, the data communication system becomes less stable, and thereliability of data communications seriously decreases.

DISCLOSURE OF THE INVENTION

The present invention is devised to solve the conventional problems andprovides a semiconductor circuit device which can obtain more stableoperations against noise in a data communication system withoutincreasing the power consumption of the overall system, therebyimproving the reliability of data communication.

In order to solve the problems, the semiconductor circuit device of thepresent invention is a semiconductor circuit device for demodulatingdigital data from a high-frequency signal having a carrierfrequency-modulated based on the digital data, comprising a digital IQdemodulator for performing quadrature demodulation on a digital signalobtained by digital conversion from an analog signal having beenobtained by frequency-converting the high-frequency signal while usingthe oscillation output of a PLL as a reference frequency signal, an F-Vconverter circuit for converting a frequency of a digital output signalfrom the digital IQ demodulator to a voltage and outputting ademodulation baseband signal corresponding to the digital data afterpassing the digital output signal through band-pass filters, a maximumvalue holding circuit for holding the maximum value of the demodulationbaseband signal outputted from the F-V converter circuit, a minimumvalue holding circuit for holding the minimum value of the demodulationbaseband signal, an averaging circuit for averaging the maximum value ofthe demodulation baseband signal and the minimum value of the basebandsignal, a frequency offset detector for detecting a frequency offsetamount on the demodulation baseband signal from the averaging circuit,and an offset correcting unit for correcting the frequency offset amounton the demodulation baseband signal by using the frequency offset amountas a feedback signal to a threshold value for deciding the data of thedemodulation baseband signal, the frequency offset amount having beendetected by the frequency offset detector.

With this configuration, a frequency offset is accurately detected witha small circuit size and fed back to a threshold value for datadecision, thereby accurately performing data decision of thedemodulation baseband signal and improving a receiving characteristic.

The semiconductor circuit device of the present invention furthercomprises a frequency converter circuit for frequency-converting thefrequency offset amount having been detected by the frequency offsetdetector, and a filter bandwidth correcting unit for correcting thebandwidth of the band-pass filter based on a frequency converted valuecorresponding to the frequency offset amount having been calculated bythe frequency converter circuit.

The semiconductor circuit device of the present invention furthercomprises a demodulator offset correcting unit for correcting thefrequency offset amount on the demodulation baseband signal for thedigital IQ demodulator based on the frequency converted valuecorresponding to the frequency offset amount having been calculated bythe frequency converter circuit.

The semiconductor circuit device of the present invention furthercomprises a PLL frequency correcting unit for controlling the frequencyof the oscillation output of the PLL and correcting the frequency offsetamount on the demodulation baseband signal based on the frequencyconverted value corresponding to the frequency offset amount having beencalculated by the frequency converter circuit.

With this configuration, it is possible to make a correction in the samedirection as the center frequency of the filter relative to the cutofffrequency of the filter, thereby improving the receiving characteristic.

The semiconductor circuit device of the present invention furthercomprises a feedback gain circuit which provides a given gain for thefrequency offset amount having been detected by the frequency offsetdetector, and uses the frequency offset amount as the feedback signal tothe threshold value for deciding the data of the demodulation basebandsignal.

With this configuration, a correction amount is adjusted by the feedbackgain circuit, thereby improving the stability of a system.

The semiconductor circuit device of the present invention furthercomprises an operation controller circuit for periodically operating thefrequency offset detector, and a timer counter for counting a duty cycleof the frequency offset detector operated by the operation controllercircuit.

The semiconductor circuit device of the present invention furthercomprises a counting period storage device for storing a set value forsetting the counting period of the timer counter at a given value.

The semiconductor circuit device of the present invention furthercomprises a frequency offset value storage device for storing thefrequency offset value having been detected by the frequency offsetdetector, and an operation controller circuit for exercising control toupdate the value of the frequency offset value storage device with agiven period.

With this operation, the system is intermittently operated arbitrarilyor automatically, thereby reducing the power consumption of the system.

The semiconductor circuit device of the present invention furthercomprises a comparator for comparing the frequency offset value havingbeen stored in the frequency offset value storage device and thefrequency offset value currently detected by the frequency offsetdetector, and a unit for deciding a change in the frequency offset valuebased on a comparison result of the comparator, causing the countingperiod storage device to store a count set value of the timer counteraccording to a decision result, and changing the duty cycle of thefrequency offset detector operated by the operation controller circuit.

The semiconductor circuit device of the present invention furthercomprises an operation controller circuit for generating a controlsignal for controlling the update of the frequency offset value, thecontrol signal being generated according to a moving direction and amovement amount decided based on the code of the frequency offset valuein the comparison result of the comparator.

With this configuration, a limit is imposed according to a change in thefrequency offset value, thereby improving the stability of the system.

The semiconductor circuit device of the present invention furthercomprises an F detector circuit for deciding the period of the timercounter, and a bit mask circuit for masking the specific bits of thedemodulation baseband signal according to the period decided by the Fdetector circuit.

With this configuration, the system is intermittently operatedarbitrarily or automatically, thereby reducing the power consumption ofthe system.

As described above, according to the present invention, a frequencyoffset is accurately detected with a small circuit size and fed back toa threshold value for data decision, thereby accurately performing datadecision of the demodulation baseband signal and improving a receivingcharacteristic.

Further, it is possible to make a correction in the same direction asthe center frequency of the filter relative to the cutoff frequency ofthe filter, thereby improving the receiving characteristic.

Moreover, a correction amount is adjusted by the feedback gain circuit,thereby improving the stability of the system.

Besides, the system is intermittently operated arbitrarily orautomatically, thereby reducing the power consumption of the system.

Additionally, a limit is imposed according to a change in the frequencyoffset value, thereby improving the stability of the system.

As described above, it is possible to prevent the accuracy of detectinga DC offset component on the demodulation baseband signal from beingreduced by the presence of noise, prevent an unstable operating statecaused by a malfunction resulting from the lower accuracy of detection,and accurately detect and correct a frequency offset component on thedemodulation baseband signal.

As a result, a data communication system can attain more stableoperations against noise without increasing the power consumption of theoverall system, thereby improving the reliability of data communication.

According to the semiconductor circuit device of the present invention,the data communication system can attain more stable operations againstnoise without increasing the power consumption of the overall system,thereby improving the reliability of data communication. In the field ofdata communication, the semiconductor circuit device is useful in acommunication system using frequency modulation, for example, FSKdemodulation. The semiconductor circuit device is particularly useful inthe field of radios requiring low cost and low power consumption in anarrow band, and thus industrially applicable.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a schematic configuration of an FSKradio using a semiconductor circuit device according to Embodiment 1 ofthe present invention;

FIG. 2 is a block diagram showing another schematic configuration of theFSK radio using the semiconductor circuit device according to Embodiment1;

FIG. 3 is a block diagram showing the configuration of a feedback gaincircuit in the semiconductor circuit device according to Embodiment 1;

FIG. 4 is a block diagram showing the schematic configuration of anintermittent operation control section in a semiconductor circuit deviceaccording to Embodiment 2 of the present invention;

FIG. 5 is a block diagram showing the configuration of a count monitorcircuit in a semiconductor circuit device according to Embodiment 3 ofthe present invention;

FIG. 6 is a block diagram showing the configuration of an average valueholding circuit in the semiconductor circuit device according toEmbodiment 3 of the present invention; and

FIG. 7 is a block diagram showing the schematic configuration of a powerconsumption reduction circuit in a semiconductor circuit deviceaccording to Embodiment 4 of the present invention.

DESCRIPTION OF THE EMBODIMENTS

A semiconductor circuit device showing embodiments of the presentinvention will be specifically discussed below with reference to theaccompanying drawings.

Embodiment 1

A semiconductor circuit device will be discussed below according toEmbodiment 1 of the present invention.

FIG. 1 is a block diagram showing a structural example of thesemiconductor circuit device according to Embodiment 1 and showing acircuit configuration for correcting a frequency offset of a receiveraccording to the FSK method in response to a data decision result.

FIG. 2 is a block diagram showing another structural example of thesemiconductor circuit device according to Embodiment 1 and showing acircuit configuration for correcting a frequency offset of the receiveraccording to the FSK method in response to an input carrier. FIG. 3 is ablock diagram showing still another structural example of thesemiconductor circuit device according to Embodiment 1 and showing acircuit configuration for stabilizing the correction of a frequencyoffset of the receiver according to the FSK method.

As shown in FIG. 1, the semiconductor circuit device has an antenna 1for receiving an FSK signal as a high-frequency signal, antenna receivedata S1 which is the FSK signal received by the antenna 1, a low noiseamplifier (LNA) 2 for amplifying the antenna receive data S1 to areceivable level, amplification receive data S2 outputted by the lownoise amplifier 2, a mixer (MIXER) 3 for frequency-converting theamplification receive data S2 to an intermediate frequency, PLL 4 forgenerating a reference frequency for the MIXER 3, a reference frequencysignal S4 generated from the PLL 4, a frequency-converted FSK signal S3with the intermediate frequency obtained by frequency-converting theamplification receive data S2 based on the reference frequency signal S4in the MIXER 3, an analog band-pass filter (BPF) 5 having anintermediate frequency band as a pass band, a filter passed FSK signalS5 obtained by removing noise through the analog BPF 5, an AD converter6 for converting the filter passed FSK signal S5 from an analog signalto a digital signal, an AD converted FSK signal S6 obtained by digitalconversion through the AD converter 6, a digital IQ demodulator 7 forperforming quadrature demodulation on the AD converted FSK signal S6 ina digital manner, an I (in-phase) signal S7 and a Q (quadrature) signalS8 which are generated by the digital IQ demodulator 7, band-passfilters 8 and 9 for band-limiting the I signal S7 and the Q signal S8with a channel width, a filter passed I signal S9 and a filter passed Qsignal S10 which have been band-limited by the band-pass filter 8, anF-V converter circuit 10 for performing baseband demodulation using thefilter passed I signal S9 and filter passed Q signal S10 which have beenobtained by channel selection, a demodulation baseband signal S11 havingundergone frequency-voltage conversion, a maximum value holding circuit11 for holing the maximum value of the demodulation baseband signal S11,a minimum value holding circuit 12 for holding the minimum value of thedemodulation baseband signal S11, an averaging circuit 13 forcalculating an average value based on a maximum held value S12 of themaximum value holding circuit 11 and a minimum held value S13 of theminimum value holding circuit 12, a frequency offset value (amount) S14which is the output of the averaging circuit 13, a data slicer 14 fordeciding the data of the demodulation base band signal S11 by using thefrequency offset value S14, and binarized demodulation data S15 havingbeen binarized by the data slicer 14.

As shown in FIG. 2, in addition to the configuration of FIG. 1, thesemiconductor circuit device has a V-F converter circuit 15 forconverting the frequency offset value S14 to a frequency, a clockgenerating section 16 serving as a filter bandwidth correcting unit forswitching the frequency of an operating clock, which is supplied to theband-pass filters 8 and 9, according to a frequency offset frequencyconverted value S16 serving as the output of the V-F converter circuitand for correcting the bandwidths of the band-pass filters 8 and 9, anda filter operating clock signal S17 outputted from the clock generatingsection 16.

Furthermore, as shown in FIG. 3, the semiconductor circuit device has afrequency offset amount S10 which is the output of the averaging circuit13, a feedback gain circuit 100 for providing the frequency offsetamount S100 with a given gain, and a feedback gain value S101 which isthe output value obtained after the feedback gain.

First, the following will discuss the specific operations of thesemiconductor circuit device shown in FIG. 1.

The FSK signal as a high-frequency signal is modulated to a carrierfrequency band and received by the antenna 1. The antenna receive dataS1, which is the received FSK signal, is amplified by the low noiseamplifier 2 to a level sufficiently enabling a demodulating operationand is outputted as the amplification receive data S2. A signal of ahigh-frequency band of MHz used in the FSK method causes a large loss indigital processing, and thus the signal is frequency-converted to anintermediate frequency of KHz by the MIXER 3. In this case, the PLL 4generates the reference frequency signal S4 as a local oscillationsignal for the MIXER 3 when the signal is frequency-converted to theintermediate frequency. By supplying the reference frequency signal S4to the MIXER 3, it is possible to perform frequency conversion to theintermediate frequency according to the reference frequency S4.

The frequency-converted FSK signal S3 having been frequency-convertedthus is converted to the filter passed FSK signal S5 by the analog BPF 5to remove a noise component and a disturbing component which areincluded in the carrier after the frequency conversion. At this point,to perform digital processing, the filter passed FSK signal S5 isdigitally converted by the AD converter 6 to the AD converted FSK signalS6. Various demodulation methods are available for the FSK signal. Inthe following explanation, a method of performing quadraturedemodulation and frequency voltage conversion by means of an IQ signalis selected as an example.

First, for quadrature demodulation, the AD converted FSK signal S6serving as a digital signal is demodulated to the I signal S7 serving asan in-phase component and the Q signal S8 serving as a quadraturecomponent by the digital IQ demodulator 7. A disturbing wave of anadjacent channel or larger is removed from the signals by the band-passfilters 8 and 9 having a bandwidth of a channel width, and the signalsare transmitted as the filter passed I signal S9 and the filter passed Qsignal S10 to the F-V converter circuit 10. The demodulation basebandsignal S11 having been converted to a voltage by the F-V convertercircuit 10 is a digital signal having a given bit range, and thedemodulation baseband signal S11 is outputted from the data slicer 14,which binarizes the signal with threshold decision, as the binarizeddemodulation data S15 serving as a digital demodulation signal.

Then, the maximum value of the demodulation baseband signal S11 servingas a digital signal is held at a given time by the maximum value holdingcircuit 11. Similarly, the minimum value of the demodulation basebandsignal S11 is held by the minimum value holding circuit 12. The maximumheld value S12 and the minimum held value S13, which are the outputs ofthe maximum value holding circuit 11 and the minimum value holdingcircuit 12, are averaged to obtain an intermediate value. This value isa displacement from 0 point and thus is outputted as the frequencyoffset amount S14 from a frequency offset detector composed of theseconstituent elements. The value of the frequency offset amount S14 istransmitted to the data slicer 14. An offset correcting unit makes itpossible to perform data decision in consideration of the frequencyoffset amount with the frequency offset amount S14 serving as athreshold value of the data decision. Since a digital value is used, thedata decision can be accurately performed.

Similarly, in FIG. 2, when the V-F converter circuit 15 forfrequency-converting the digital value of the frequency offset amountS14 makes a conversion in, e.g., kHz, the V-F converter circuit 15 usesa frequency conversion method of using the mask of a bit of thefrequency offset amount S14 or a table reference with the resolvingpower of the frequency offset amount S14, and the V-F converter circuit15 outputs a corresponding frequency value instead of the digital valueof the frequency offset amount S14. The output of the V-F convertercircuit 15 is the frequency offset frequency converted value S16. Whenthe frequency offset frequency converted value S16 is sent to the clockgenerating section 16 for supplying a clock to the band-pass filters 8and 9, the frequency division ratio of a clock frequency is switchedaccording to the value, so that clock frequencies to be supplied to theband-pass filters 8 and 9 is switched.

The band-pass filters 8 and 9 can arbitrarily switch the cutofffrequencies of the filters according to the clock frequencies of thefilters as long as the band-pass filters 8 and 9 are filters like a CICfilter whose filter characteristic is determined by a clock frequency. Aclock frequency generated in the clock generating section 16 is switchedaccording to the frequency offset, so that it is possible to shift thecenter frequencies of the filters, prevent the FSK signal from beingdegraded by the attenuation of the filters, and prevent degradation of areceiving characteristic.

Further, the frequency offset frequency converted value S16 is fed backto the digital IQ demodulator 7 and quadrature demodulation is performedby a phase change of 0 and 90 degrees. In this case, a demodulatoroffset correcting unit multiplies, with the value S16, a frequency shiftequivalent to the frequency offset and corrects the frequency offsetamount on the demodulation baseband signal for the digital IQdemodulator. For example, this correction can be performed by using asin table or the like and performing a multiplication of sin and cosaccording to the frequency.

Furthermore, the frequency offset frequency converted value S16 is fedback to the PLL 4 and a reference frequency generated in a prescaler inthe PLL 4 is shifted according to the frequency offset by a PLLfrequency correcting unit, so that a frequency obtained in considerationof the frequency offset is outputted as the reference frequency signalS4 from the PLL 4. The frequency to be frequency-converted by the MIXER3 is obtained in consideration of the frequency offset, therebycorrecting the frequency offset of the overall system. Thus, it ispossible to prevent degradation of the FSK signal and the receivingcharacteristic.

In FIG. 3, regarding the frequency offset amount S100, for example, themaximum held value S12 serving as the maximum output may have an offsetof 400 Hz due to noise, though an actual offset is 100 Hz. In this case,when 400 Hz is immediately fed back to the detected offset, a correctionis made to a frequency displaced from the actual frequency by 300 Hz,resulting in an unstable system.

Hence, the feedback gain circuit 100 is provided with a given feedbackgain value. For example, in feedback to the detected frequency offsetamount S100 detected as one eighth, an offset amount of 50 Hz is fedback. Thus, it is possible to make a correction closer to the actualfrequency and achieve stable operations in the system.

According to an actual system, a gain is increased for high noise, and again is reduced in a place where stable signal reception is expected.Thus, it is possible to more accurately correct a frequency offset in aplace where stable signal reception is expected.

Embodiment 2

A semiconductor circuit device will be discussed below according toEmbodiment 2 of the present invention.

FIG. 4 is a block diagram showing a structural example of thesemiconductor circuit device according to Embodiment 2. As shown in FIG.4, the semiconductor circuit device has an operation controller circuit201 for controlling the operation of a frequency offset detector bymasking the output of a demodulation baseband signal S11, a timercounter 202 for generating the duty cycle of the operation controllercircuit 201, a CAP register 203 serving as a counting period storagedevice capable of setting a given counting period for the timer counter202, a timer count value register output S205 which is the output of theCAP register 203, a timer period signal S204 which is an operationenabling signal from the timer counter 202, a masked demodulationbaseband signal S201 from the operation controller circuit 201, afrequency offset amount S202 which is the output of an averaging circuit13, a holding circuit update enabling signal S206 which is a capturingtiming signal from the operation controller circuit 201, a holdingcircuit 204 serving as a frequency offset value storage device forstoring the frequency offset amount S202, which is an averaged output,according to the timing of the holding circuit update enabling signalS206, and a holding circuit held value S203 which is the output of theholding circuit 204.

First, the following will discuss the specific operations of thesemiconductor circuit device shown in FIG. 4.

The timer counter 202 makes a count with a given period and outputs thetimer period signal S204, which is an operation enabling signal, foreach period. In response to the timer period signal S204 which is anoperation enabling signal, the operation controller circuit 201 sends amasked demodulation baseband signal S11 to a maximum value holdingcircuit 11 and a minimum value holding circuit 12. With this operation,the frequency offset amount S202, which is an averaged output, isoutputted and held by the holding circuit 204. The time when thefrequency offset amount S202 is captured by the holding circuit 204(update period) is held according to the timing of the holding circuitupdate enabling signal S206 which is the capturing timing signaloutputted from the operation controller circuit 201. Hence, anintermittent operation can be performed with the period of the timercounter 202.

A given value is set for the CAP register 203 by means of software. Theset value is loaded in the timer counter 202 at a given timing. Thetimer counter 202 operates according to the loaded period and similarlycontrols the masked demodulation baseband signal S201, which is anoperation enabling control signal, and the holding circuit updateenabling signal S206. This configuration can reduce the powerconsumption of the circuit. With the timer counter value set register203, a given period can be set by software. When the stability of thesystem is confirmed by software, power consumption can be reduced in aprogrammable manner by increasing an intermittent operation period.

Embodiment 3

A semiconductor circuit device will be discussed below according toEmbodiment 3 of the present invention.

FIG. 5 is a block diagram showing a structural example of thesemiconductor circuit device according to Embodiment 3. FIG. 6 is ablock diagram showing another structural example of the semiconductorcircuit device according to Embodiment 3.

As shown in FIG. 5, the semiconductor circuit device has a comparator301 for comparing a frequency offset amount S202 serving as an averagedoutput and a holding circuit held value S203 of a holding circuit 204, acomparative value S301, a count monitor circuit 302 for deciding themovement amount of a frequency offset value according to the comparativevalue S301, and a movement amount decision result S302 which is acontrol signal from the count monitor circuit 302. Further, as shown inFIG. 6, the semiconductor circuit device has a monitor circuit 401 fordeciding the moving direction and the movement amount of a frequencyoffset according to the comparative value S301, and a movementdirection/amount decision result S401 serving as an output signal fromthe monitor circuit 401 and a holding circuit update enabling signal forthe holding circuit 204.

The following will discuss the specific operations of the semiconductorcircuit device shown in FIG. 5.

In FIG. 5, as described in Embodiment 2, by arbitrarily setting theperiod of a timer counter 202, a circuit operation is intermittentlyperformed and thus power consumption is reduced. In this case, powerconsumption is reduced by automatically detecting a stable state of asystem and automatically switching a timer counter period. To bespecific, a comparison is made between the holding circuit held valueS203 of the holding circuit 204 and the frequency offset amount S202which is the output from the averaging circuit 13 before being held,that is, current data and data one period before are compared with eachother on a time base by the comparator 301. The comparator outputs thecomparative value S301.

In this case, a difference is obtained. It is not particularly necessaryto obtain a difference. Based on the comparative value S301, the countermonitor circuit 302 controls the value of the timer counter 202according to a movement amount. For example, when a movement amountdecreases, the period of the timer counter 202 is increased to reducepower consumption. When a movement amount increases, a person on theother end may be changed or other factors may affect the movementamount, and thus the operating period of the timer counter 202 isshortened and the holding circuit is updated more frequently. Hence, thepower consumption of the circuit can be automatically reduced.

The following will discuss the specific operations of the semiconductorcircuit device shown in FIG. 6.

In FIG. 6, a unit for deciding a moving direction is added to theconfiguration of FIG. 5. That is, in the monitor circuit 401, the movingdirection of a frequency offset, to be specific, the code of the mostsignificant bit is decided for the comparative value S301 from thecomparator 301. When the code is reversed and a movement amount islarge, the moving direction/amount decision result S401 serving as aheld value update enabling signal is not issued and the current heldvalue is held by an operation controller circuit 201. With thisoperation, it is possible to prevent oscillation of a corrected value,thereby achieving a more stable system.

Embodiment 4

A semiconductor circuit device will be discussed below according toEmbodiment 4 of the present invention.

FIG. 7 is a block diagram showing a structural example of thesemiconductor circuit device according to Embodiment 4. As shown in FIG.7, the semiconductor circuit device has a timer counter period signalS501 which is a period signal from a timer counter 202, an F detectorcircuit 501 for deciding the period of the timer counter 202 based onthe timer counter period signal S501, a period decision result S502which is a control signal from the F detector circuit 501, a bit maskcircuit 502 for bit masking on a demodulation baseband signal S2011 froman operation controller circuit 201 in response to the period decisionresult S502, and bit mask data S503 which is the output of the bit maskcircuit.

The following will discuss the specific operations of the semiconductorcircuit device shown in FIG. 7.

In FIG. 7, the period of the timer counter 202 is automatically switchedaccording to the timer counter period control signal of a movementamount decision result S302 outputted by a count monitor circuit 302.The F detector circuit 501 decides a counting period based on the timercounter period signal S501 from the timer counter 202. When the Fdetector circuit 501 decides that the period is larger than apredetermined criterion of decision, it is decided that a stableoperation is performed and the F detector circuit 501 sends the perioddecision result S502 as a control signal. The period decision resultS502 is a control signal indicating that the period is stabilized andincreased. When a stable state of a system is detected based on theperiod decision result S502, the bit mask circuit 502 masks lower-orderbits and monitors only higher-order bits.

With these operations, the power consumption of the circuit is reduced.Additionally, the maximum value and the minimum value are changed onlywhen several higher-order bits move, that is, only when a large changeis found. The bit mask data S503 masked by the bit mask circuit 502 is asignal of only several bits and thus has no lower-order bits. When onlya small change is found, the bits do not change and thus powerconsumption is reduced during a circuit operation. Further, an averagedoutput is not changed, so that a frequency offset amount hardly changes.This circuit makes it possible to reduce an operating current for astable operation.

1-11. (canceled)
 12. A semiconductor circuit for demodulating ahigh-frequency signal into digital data, comprising: an AD converterconverting an analog signal into a digital signal, a digital IQdemodulator performing quadrature demodulation on the digital signal, anF-V converter circuit converting a frequency of an output signal fromthe digital IQ demodulator into a voltage and outputting a convertedsignal as a demodulation baseband signal, a frequency offset detectoroutputting a frequency offset amount given by averaging a maximum valueof the demodulation baseband signal and a minimum value of thedemodulation baseband signal, and an offset corrector correcting afrequency offset on the demodulation baseband signal by using thefrequency offset amount.
 13. The semiconductor circuit according toclaim 12, further comprising: a mixer converting a frequency of thehigh-frequency signal into an intermediate frequency between thefrequency of the high-frequency signal and a frequency of a referencefrequency signal, and a PLL generating the reference frequency signal.14. The semiconductor circuit according to claim 13, further comprisinga PLL frequency corrector correcting a frequency of the frequencyreference signal by using the frequency offset amount.
 15. Thesemiconductor circuit according to claim 12, further comprising afeedback gain circuit using the frequency offset amount as a feedbacksignal to a threshold value for deciding data of the demodulationbaseband signal.
 16. The semiconductor circuit according to claim 12,further comprising a feedback gain circuit providing a feedback signal,which is the frequency offset amount multiplied by a gain, to athreshold value for deciding data of the demodulation baseband signal.17. The semiconductor circuit according to claim 12, further comprisingan operation controller circuit periodically operating the frequencyoffset detector, and a timer counter counting a duty cycle of thefrequency offset detector.
 18. The semiconductor circuit according toclaim 17, further comprising a counting period storage device storing avalue for setting a counting period of the timer counter at the value.19. The semiconductor circuit according to claim 18, further comprisinga frequency offset amount storage device storing the frequency offsetamount as a frequency offset value, wherein the operation controllercircuit updates the frequency offset value.
 20. The semiconductorcircuit according to claim 19, further comprising a comparatoroutputting a comparative value between the frequency offset value in thefrequency offset amount storage device and the frequency offset amountcurrently outputted by the frequency offset detector.
 21. Thesemiconductor circuit according to claim 20, wherein the counting periodstorage device stores a count set value according to the comparativevalue, and the operation controller circuit changes the duty cycle ofthe frequency offset detector.
 22. The semiconductor circuit accordingto claim 21, wherein the operation controller circuit generates acontrol signal according to the comparative value for controlling updateof the frequency offset value.
 23. The semiconductor circuit accordingto claim 17, further comprising an F detector circuit deciding a periodof the timer counter, and a bit mask circuit masking specific bits ofthe demodulation baseband signal according to the period decided by theF detector circuit.